HMCC heralds 2013 as turning point

USA & SOUTH KOREA: More than 100 developer and adopter members of the Hybrid Memory Cube Consortium (HMCC) have reached consensus for the global standard that will deliver a much-anticipated, disruptive memory computing solution.

Developed in only 17 months, the final specification marks the turning point for designers in a wide range of segments--from networking and high-performance computing, to industrial and beyond--to begin designing Hybrid Memory Cube (HMC) technology into future products.

A major breakthrough with HMC is the long-awaited utilization of advanced technologies to combine high-performance logic with state-of-the-art DRAM. With this first HMC milestone reached so quickly, consortium members have elected to extend their collaborative effort to achieve agreement on the next generation of HMC interface standards.

One of the primary challenges facing the industry--and a key motivation for forming the HMCC--is that the memory bandwidth required by high-performance computers and next-generation networking equipment has increased beyond what conventional memory architectures can efficiently provide.

The term "memory wall" has been used to describe this challenge. Breaking through the memory wall requires an architecture such as HMC that can provide increased density and bandwidth with significantly lower power consumption.

The HMC standard focuses on alleviating an extremely challenging bandwidth bottleneck while optimizing the performance between processor and memory to drive high-bandwidth memory products scaled for a wide range of applications. The need for more efficient, high-bandwidth memory solutions has become particularly important for servers, high-performance computing, networking, cloud computing and consumer electronics.

The achieved specification provides an advanced, short-reach (SR) and ultra short-reach (USR) interconnection across physical layers (PHYs) for applications requiring tightly coupled or close-proximity memory support for FPGAs, ASICs and ASSPs, such as high-performance networking, and test and measurement.

The next goal for the consortium is to further advance standards designed to increase data rate speeds from 10, 12.5 and 15 gigabits per second (Gb/s) up to 28 Gb/s for SR and from 10 Gb/s up to 15 Gb/s for USR. The next-generation specification is projected to gain consortium agreement by the first quarter of 2014.